Buffer circuits (e.g., output buffers, input buffers and bidirectional buffers) are employed in a variety of electronic devices and applications. In certain applications, a buffer circuit may be subjected to a voltage potential that is substantially higher than that which is supported by the specific process technology used to fabricate the buffer circuit. For example, a buffer circuit fabricated using a 3.3 volt (V) process may be subjected to a 5.0V input signal. In order to avoid over-stressing the devices in the buffer circuit, an N-channel metal-oxide-semiconductor (NMOS) protection device, M5, gated by a supply voltage VDD of the buffer circuit 100, may be placed in series between an input pad (PAD) 102 and the remainder 104 of the buffer circuitry, as shown in FIG. 1. The inclusion of the NMOS device, however, significantly restricts an input voltage swing of the buffer circuit, which slows down the buffer speed, particularly at lower supply voltages (e.g., about 2.0V). Additionally, the NMOS device limits the minimum VDD range under which the buffer circuit will properly function to less than about two volts.
Adding a series NMOS protection device between the input pad 102 and the remainder of the buffer circuitry can also cause the buffer circuit to consume significant direct current (DC) power, for example when an input signal applied to the buffer circuit is a logic high level. Specifically, when a logic high signal is applied to the input pad 102 of the buffer circuit 100, which is connected to a first terminal (e.g., drain) of the NMOS device M5, a second terminal (e.g., source) of the device at node N2 will be about a threshold voltage (Vtn) below the supply voltage, or VDD-Vtn. Consequently, a P-channel metal-oxide semiconductor (PMOS) transistor device (e.g., M1) in a first stage of the buffer circuit 100 connected to the series protection device M5 at node N2, may not completely turn off, thereby creating a DC path between VDD and ground. Moreover, if the first stage of the buffer circuit, including NMOS device M2 and PMOS device M1, incorporates a low pass filter therein, as is often required in certain applications, a delay through the filter would vary as a function of the incoming bit patterns applied to the buffer circuit, which is undesirable. While it is known to add a PMOS transistor device in parallel with the NMOS device M5 in order to reduce DC power consumption in the buffer circuit when a logic high input signal is applied, this PMOS device is only weakly turned on, and therefore such approach does not improve the speed of the buffer circuit.
Accordingly, there exists a need for an improved buffer circuit that provides protection against overvoltage stress, and yet does not suffer from one or more of the problems exhibited by conventional buffer circuits.